An apparatus, a method and a system for performing instructions and logic to perform floating-point and integer operations for machine learning
One embodiment provides for a processing unit comprising fetch and decode circuitry to fetch and decode a floating-point multiply-accumulate instruction; and execution circuitry to execute the floating-point multiply-accumulate instruction. The execution circuitry comprises mantissa multiplication c...
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Main Authors | , , , , , , , , , , , , , , , , , , |
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Format | Patent |
Language | Chinese English |
Published |
21.10.2023
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Subjects | |
Online Access | Get full text |
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Summary: | One embodiment provides for a processing unit comprising fetch and decode circuitry to fetch and decode a floating-point multiply-accumulate instruction; and execution circuitry to execute the floating-point multiply-accumulate instruction. The execution circuitry comprises mantissa multiplication circuitry, wherein the mantissa multiplication circuitry is shared with an integer datapath of the execution circuitry, wherein responsive to the floating-point multiply-accumulate instruction, the mantissa multiplication circuitry is to perform a multiplication operation with a mantissa value of each 16-bit floating-point data element of a first plurality of 16-bit floating-point data elements and a mantissa value of a corresponding 16-bit floating-point data element of a second plurality of 16-bit floating-point data elements to generate a corresponding plurality of mantissa results; exponent processing circuitry, responsive to the floating-point multiply-accumulate instruction, to perform an operation with an exp |
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Bibliography: | Application Number: TW202211130374 |