Apparatus and system for improvingbranch prediction throughput by ski pping over cachelines without branches

According to one general aspect, an apparatus may include a branch prediction circuit configured to predict if a branch instruction will be taken or not. The apparatus may include a branch target buffer circuit configured to store a memory segment empty flag that indicates whether or not the memory...

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Main Authors GOVINDAN, MADHU SARAVANA SIBI, TKACZYK, MONIKA, CHANGWATCHAI, WICHAYA TOP, ZURASKI, GERALD DAVID, ZOU, FUZHOU, NGO, ANHDUNG
Format Patent
LanguageChinese
English
Published 01.08.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:According to one general aspect, an apparatus may include a branch prediction circuit configured to predict if a branch instruction will be taken or not. The apparatus may include a branch target buffer circuit configured to store a memory segment empty flag that indicates whether or not the memory segment after a target address includes at least one other branch instruction, wherein the memory segment empty flag was created during a commit stage of a prior occurrence of the branch instruction. The branch prediction circuit may be configured to skip over the memory segment if the memory segment empty flag indicates a lack of other branch instruction(s).
Bibliography:Application Number: TW20209113405