Method of correcting wiring of semiconductor package

• Main Authors: KIM, DAE OK, WAKABAYASHI, SHINICHI, KIM, BOK MUN
• Format: Patent
• Language: Chinese; English
• Published: 01.08.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES; MEASURING; PHYSICS; SEMICONDUCTOR DEVICES; TESTING

The present invention relates to a method of correcting wiring of a semiconductor package, and more particularly, to a method of correcting wiring of a semiconductor package, in which a location of an integrated circuit chip and a location of a bonding pad are checked through an image in a semiconductor packaging process, a difference between a design location and an actual location is calculated as a numerical value, and a wiring pattern stored in a database is corrected according to a displacement mount, thereby preventing defects from being generated in the forming of the wiring between a ball pad and the bonding pad. According to the present invention, it is possible to accurately recognize an actual seating location of a chip in a wiring exposure process of a semiconductor chip and achieve an accurate wiring connection by transforming a wiring pattern by an error between a design location and an actual location.