Identifying nuisances and defects of interest in defects detected on a wafer

• Main Authors: DUFFY, BRIAN, SAH, KAUSHIK, VON DEN HOFF, MIKE, MANI, ANTONIO, CROSS, ANDREW JAMES, PLIHAL, MARTIN
• Format: Patent
• Language: Chinese; English
• Published: 01.01.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES; MEASURING; PHYSICS; SEMICONDUCTOR DEVICES; TESTING

Methods and systems fir identifying nuisances and defects of interest (DOIs) in defects detected on a wafer are provided. One method includes acquiring metrology data for the wafer generated by a metrology tool that performs measurements on the wafer at an array of measurement points. In one embodiment, the measurement points are determined prior to detecting the defects on the wafer and independently of the defects detected on the wafer. The method also includes determining locations of defects detected on the wafer with respect to locations of the measurement points on the wafer and assigning metrology data to the defects as a defect attribute based on the locations of the defects determined with respect to the locations of the measurement points. In addition, the method includes determining if the defects are nuisances or DOIs based on the defect attributes assigned to the defects.