Apparatus for multi-core commun[catjon acceleration using hardware queue device

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ("LLC"), and a har...

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Main Authors WILKINSON, HUGH, CLEE, JAMES T, VANGATI, NARENDER, BERNSTEIN, DEBRA, VERPLANKE, EDWIN, WANG, YIPENG, CUNNINGHAM, ANDREW, HERDRICH, ANDREW J, BURROUGHS, WILLIAM G, MILLER, STEPHEN H, MA, TE K, HASTING, JOSEPH R, RICHARDSON, BRUCE, TSAI, JR-SHIAN, SONNIER, DAVID, MCDONNELL, NIALL D, WHITESELL, JAMISON, YAN, AN, VENKATESAN, NAMAKKAL N, VAN DOREN, STEPHEN R, BURRES, BRADLEY A, PIROG, JERRY, TAI, TSUNG-YUAN CHARLES, WANG, REN, EADS, GAGE W, KENNY, JONATHAN
Format Patent
LanguageChinese
English
Published 01.07.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ("LLC"), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.
Bibliography:Application Number: TW20165139954