Method of making oxide thin film transistor array, and device incorporating the same

• Main Author: DEN BOER, WILLEM
• Format: Patent
• Language: Chinese; English
• Published: 01.11.2018
• Subjects: BASIC ELECTRIC ELEMENTS; CHEMICAL SURFACE TREATMENT; CHEMISTRY; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING MATERIAL WITH METALLIC MATERIAL; COATING METALLIC MATERIAL; DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING; DIFFUSION TREATMENT OF METALLIC MATERIAL; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FREQUENCY-CHANGING; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL; METALLURGY; NON-LINEAR OPTICS; OPTICAL ANALOGUE/DIGITAL CONVERTERS; OPTICAL LOGIC ELEMENTS; OPTICS; PHYSICS; SEMICONDUCTOR DEVICES; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF

Certain example embodiments relate to methods of making oxide thin film transistor arrays (e.g., IGZO, amorphous or polycrystalline ZnO, ZnSnO, InZnO, and/or the like), and devices incorporating the same. Blanket layers of an optional barrier layer, semiconductor, gate insulator, and/or gate metal are disposed on a substrate. These and/or other layers may be deposited on a soda lime or borosilicate substrate via low or room temperature sputtering. These layers may be later patterned and/or further processed in making a TFT array according to certain example embodiments. In certain example embodiments, all or substantially all TFT processing may take place at a low temperature, e.g., at or below 150 degrees C., until a post-annealing activation step, and the post-anneal step may take place at a relatively low temperature (e.g., 200-250 degrees C.).