Embedded substrate package structure

• Main Authors: ZHANG, FENG-YI, HOU, JUN-YUAN, WANG, DONGUAN, YUAN, XI-YING, HE, SONG-LIAN
• Format: Patent
• Language: Chinese; English
• Published: 21.10.2018
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Provided is an embedded substrate package structure, including, from top to bottom, a fourth dielectric layer, a second substrate, a chip with a fifth dielectric layer, a third dielectric layer, a second dielectric layer, a first substrate and a first dielectric layer; wherein the substrates are disposed respectively with wire layers and through holes, and each of dielectric layers is disposed with openings, conductive bumps or conductive pads, wire layers, through holes, and chip to collectively form electrical connection. The chip is electrically connected to the substrate in a flip-chip manner, and the back of the chip interfaces a dielectric layer. Compared to the prior art which chip bonding is in face-up mode, the packaging structure with the face-down chip of the present invention can simplify the manufacturing process by the flip-chip method.