Interference testing

In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the v...

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Main Authors NAIGER, DANNY, KOSTINSKY, ALEXEY, MOZAK, CHRISTOPHER P, LEVY, TOMER, CHESES, PAUL S, ABOULENEIN, NAGI, SHEHADI, JAMES M, SCHOENBORN, THEODORE Z
Format Patent
LanguageChinese
English
Published 01.07.2017
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Summary:In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.
Bibliography:Application Number: TW20154106287