Interference testing
In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the v...
Saved in:
Main Authors | , , , , , , , |
---|---|
Format | Patent |
Language | Chinese English |
Published |
01.07.2017
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described. |
---|---|
Bibliography: | Application Number: TW20154106287 |