Highly scalable single-poly non-volatile memory cell
A nonvolatile memory cell (1) includes a semiconductor substrate (100), a first OD region (210), a second OD region (220), an isolation region (200) separating the first OD region (210) from the second OD region (220), a PMOS select transistor (10) disposed on the first OD region (210), and a PMOS f...
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Main Authors | , , |
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Format | Patent |
Language | Chinese English |
Published |
01.04.2017
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Subjects | |
Online Access | Get full text |
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Summary: | A nonvolatile memory cell (1) includes a semiconductor substrate (100), a first OD region (210), a second OD region (220), an isolation region (200) separating the first OD region (210) from the second OD region (220), a PMOS select transistor (10) disposed on the first OD region (210), and a PMOS floating gate transistor (20) serially connected to the PMOS select transistor (10) on the first OD region (210). The PMOS floating gate transistor (20) includes a floating gate (120) overlying the first OD region (210). A memory P well (102) is disposed in the semiconductor substrate (100). A memory N well (104) is disposed in the memory P well (102). The memory P well (102) overlaps with the first OD region (210) and the second OD region (220). The memory P well (102) has a junction depth (d1) that is deeper than a trench depth (d) of the isolation region (200). The memory N well (104) has a junction depth (d2) that is shallower than the trench depth (d) of the isolation region (200). |
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Bibliography: | Application Number: TW20154119498 |