Memory array on more than one die and method for accessing it

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital sign...

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Bibliographic Details
Main Authors LOH, GABRIEL H, DEVALE, JOHN P, TAUFIQUE, MOHAMMED H, JALLICE, DERWIN, BLACK, BRYAN, BREKELBAUM, EDWARD A, RUPLEY, JEFFREY P, MCCAULEY, DONALD W
Format Patent
LanguageChinese
English
Published 11.08.2013
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
Bibliography:Application Number: TW200897124276