Method of making a dual strained channel semiconductor device

According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integrati...

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Main Authors THOMAS, SHAWN G, WHITE, TED R, SADAKA, MARIAM G, BARR, ALEXANDER L, NGUYEN, BICH-YEN, JOVANOVIC, DEJAN, THEAN, VOON-YEW
Format Patent
LanguageChinese
English
Published 11.03.2013
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
Bibliography:Application Number: TW200695107353