Electromagnetic noise shielding in semiconductor packages using caged interconnect structures

A semiconductor device has a die ( 10 ) overlying and electrically connected to a support structure ( 11 ), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects ( 32, 38 ) are noise sources to victim interconnects ( 29, 59 ) carrying sensitive signals. An ar...

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Bibliographic Details
Main Authors ZHOU, YAPING, JOINER, BENNETT A, HERBERG, BEN W
Format Patent
LanguageChinese
English
Published 21.05.2012
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Online AccessGet full text

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Summary:A semiconductor device has a die ( 10 ) overlying and electrically connected to a support structure ( 11 ), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects ( 32, 38 ) are noise sources to victim interconnects ( 29, 59 ) carrying sensitive signals. An arrangement of shield interconnects ( 51-58 ) surround the victim interconnect ( 29, 59 ) in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e.g. bump) is applicable.
Bibliography:Application Number: TW20040131220