An article having multilayer dielectric stack

This invention relates to a method of dual damascene integration for manufacture of integrating circuits using three top hard mask layers having alternating etch selectivity characteristics.

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Bibliographic Details
Main Authors LYNNE K. MILLS, PAUL H- TOWNSEND, JOOST J. M. WAETERLOOS, RICHARD J. STRITTMATTER
Format Patent
LanguageEnglish
Published 21.12.2010
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:This invention relates to a method of dual damascene integration for manufacture of integrating circuits using three top hard mask layers having alternating etch selectivity characteristics.
Bibliography:Application Number: TW200392107415