Method and system for providing fast design for testability prototyping in integrated circuit designs

• Main Authors: HUANG, STEVE C, CHEN, IHAO, FAN, YONG
• Format: Patent
• Language: English
• Published: 11.02.2007
• Subjects: BASIC ELECTRIC ELEMENTS; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; PHYSICS; SEMICONDUCTOR DEVICES

Method and system for providing a computer implemented process of performing design for testability analysis and synthesis in an integrated circuit design. The method includes partitioning each logic block in an integrated circuit design based on one or more boundaries of multi-cycle initial setup sequence, excluding the one or more logic blocks with multi-cycle initial setup sequence from valid candidate blocks, selecting a constraint setting set, extracting a subset of constraint settings from the selected constraint setting set, applying the extracted subset of constraint settings to the integrated circuit design, performing design for testability analysis and synthesis on the valid candidate blocks, performing scan cell replacement. Scan cell replacement may include performing class selection based on affinity between cells, determining a target characterization for the scan cell replacement, and replacing one or more cells with a corresponding one or more scan cells having the closest target characteristics.