Method of fabricating under bump metallurgy structure and semiconductor wafer with solder bumps

• Main Authors: SUO, CHAO-DUNG, KUO, KUEI-HSIAO, HUANG, YU-HUNG
• Format: Patent
• Language: English
• Published: 11.10.2005
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method for fabricating under bump metallurgy (UBM) and a semiconductor wafer with a plurality of solder bumps are proposed. The method includes preparing a wafer having a plurality of electrically connecting pads formed thereon; depositing an adhesive metal layer, such as aluminum layer, on each electrically connecting pad to provide metal layers coating; and stacking at least one barrier layer (e.g. nickel layer) and at least one solder wettable layer (e.g. copper layer) onto the adhesive metal layer, cooperating with the adhesive metal layer to form an under bump metallurgy structure for solder bumps bonding. The barrier layer and the solder wettable layer are stacked alternatively so as to increase the buffer capacity of the barrier layer to avoid bad bump soldering due to the consumption of barrier layer and to reduce stress of the UBM structure to prevent warpage of wafer.