MOS-type variable capacitance element

• Main Authors: OGAWA, TAKAOKI, AOKI, KOJU, TOMITA, KAZUHIRO
• Format: Patent
• Language: English
• Published: 01.10.2004
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

In the invention, an n-well (3) is formed in a p-type semiconductor substrate (2). A gate insulating film (4) is formed on the p-type semiconductor substrate (2) and the n-well (3). A gate electrode (6) is formed on the gate insulating film (4). A source layer (8), which is selectively diffused with a high concentration of n-type impurities and is adjacent to the gate insulating film (4), is formed on the surface of p-type semiconductor substrate (2), the n-well (3) and a region extending over both the p-type semiconductor substrate (2) and the n-well (3). Additionally, a contact layer (11), which is apart from the source layer (8) and is selectively diffused with a high concentration of p-type impurities, is formed. By applying a terminal-to-terminal voltage VT between the source layer (8) and the gate electrode (6), a capacitance characteristic of good linearity in a wide range with respect to the terminal-to-terminal voltage VT is achieved. The invention provides a kind of MOS variable capacitive element that has a good linear characteristic in a wide range with respect to the terminal-to-terminal voltage VT as well as the performance improvement of a VCO circuit. In addition, the invented MOS variable capacitive element has a simple structure and can be produced without the need of any extra mask and manufacturing steps.