Bumping process

• Main Author: LIN, YUEH-LUNG
• Format: Patent
• Language: English
• Published: 01.08.2004
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A bumping process is described. The bumping process comprises the following steps: (a) Providing a wafer that has a plurality of bonding pads and a passivation layer. The passivation layer exposes the bonding pads; (b) Forming a metal layer on the wafer that at least covers the bonding pads; (c) Forming a positive photoresist layers on the wafer; (d) Forming a plurality of first openings corresponding to the bonding pads in the positive photoresist layer respectively to expose the metal layer; (e) Forming a negative photoresist layers on the patterned positive photoresist layer; (f) Forming a plurality of second openings corresponding to the bonding pads in the negative photoresist layer respectively; (g) Filling the solder material into each of the first openings and the second openings to form a plurality of solder posts; (h) Removing the positive photoresist layer and the negative photoresist layer. The bumping process can prevent the decrease in height of bumps caused by undercut and further increase the height of bumps to enhance the reliability of the connection between chip and carrier.