Double densed core gates in SONOS flash memory

A method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric (114) over a substrate (112); forming a first set of memory cell gates (116) over the charge trapping dielectric (114) in a core region; forming a conformal insulation material layer (118)...

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Bibliographic Details
Main Authors RAMSBEY, MARK T, VAN BUSKIRK, MICHAEL A, SUN, YU
Format Patent
LanguageEnglish
Published 11.05.2004
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric (114) over a substrate (112); forming a first set of memory cell gates (116) over the charge trapping dielectric (114) in a core region; forming a conformal insulation material layer (118) around the first set of memory cell gates (116); and forming a second set of memory cell gates (122) in the core region, wherein each memory cell gate of the second set of memory cell gates (122) is adjacent to at least one memory cell gate of the first set of memory cell gates (116), each memory cell gate of the first set of memory cell gates (116) is adjacent at least one memory cell gate of the second set of memory cell gates (122), and the conformal insulation material layer (118) is positioned between each adjacent memory cell gate is disclosed.
Bibliography:Application Number: TW200291122815