Digital baseband system
The invention provides a baseband system for a short-range radio communication system. It is conform to the Bluetooth baseband specification and is well-suited for an efficient hardware implementation, providing a low-power, small-sized, and low-cost radio subsystem design. The baseband system compr...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
21.12.2003
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | The invention provides a baseband system for a short-range radio communication system. It is conform to the Bluetooth baseband specification and is well-suited for an efficient hardware implementation, providing a low-power, small-sized, and low-cost radio subsystem design. The baseband system comprises a transceiver unit and a buffer unit, whereby the system has an efficient gate count and a reduced power consumption. The transceiver unit design is based on a pipelined signal processing with distributed data path flow control. The transceiver unit processes outgoing and incoming packets, and comprises a plurality of signal processing units connected in sequence, whereby each signal processing unit is clocked by a common clock signal. A mode line is connected to each signal processing unit for switching each signal processing unit between a transmit mode and a receive mode. A control line to which each signal processing unit is connected communicates flow control information either in the transmit mode to one or more of the preceding signal processing units or in the receive mode to one or more of the following signal processing units. The buffer unit comprises a buffer system that applies a flexible memory organization concept, which leads to an efficient implementation of buffers or storage elements in terms of gate count and power consumption, and offers the flexibility to dynamically allocate memory for variable length user packets. The buffer system for storing data of the first processing unit and second processing unit comprises a plurality of storage elements, whereby each storage element has a first storage unit and a second storage units. A switch subsystem is provided for switching each storage element between first and second modes. In the first mode each first storage unit is addressable by the first processing unit and each second storage unit is addressable by the second processing unit. In the second mode each second storage unit is addressable by the first processing unit and each first storage unit is addressable by the second processing unit. |
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Bibliography: | Application Number: TW200190115991 |