Phase detector architecture for phase error estimating and zero phase restarting

• Main Authors: STASZEWSKI, ROBERT B, SPAGNA, FULVIO
• Format: Patent
• Language: English
• Published: 21.08.2003
• Edition: 7
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; INFORMATION STORAGE; INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A system and method for enabling an efficient zero phase restart (ZPR) of a device. The structure is based on deploying normalized timing gradient (NTG) blocks (501 and 502) in pairs, each circuit employing an orthogonal phase error transfer function characteristic (having one TG circuit sample orth...