Phase detector architecture for phase error estimating and zero phase restarting

• Main Authors: STASZEWSKI, ROBERT B, SPAGNA, FULVIO
• Format: Patent
• Language: English
• Published: 21.08.2003
• Edition: 7
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; INFORMATION STORAGE; INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A system and method for enabling an efficient zero phase restart (ZPR) of a device. The structure is based on deploying normalized timing gradient (NTG) blocks (501 and 502) in pairs, each circuit employing an orthogonal phase error transfer function characteristic (having one TG circuit sample orthogonally in relation to the other), for example, PR4 and EPR4 modes ideal sampling instances of a preamble. Through iteration of the method of the invention, an NTG block (501 or 502) is selected based on having a native timing sampling instance with a phase error that is closest to zero. Since there is an equal chance that either of the circuits in a circuit pair will be selected, if the circuit implementing the current non-native architecture is selected, a separate signal is generated. This signal adds the equivalent of 180 DEG to the error value that is provided to the timing recovery circuit. For example, by iterating the process after the special case of a zero phase restart (ZPR) operation, the native sampling instance is ""forced"" to be selected thereafter.