Thin film transistor array panels for liquid crystal display and manufacturing methods of the same

• Main Authors: SANG, KIM-IL, HONG, WAN-SIK, HONG, MUN-PYO, KYO, CHINKEI, RO, SUIKI
• Format: Patent
• Language: English
• Published: 21.05.2003
• Edition: 7
• Subjects: DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL ANALOGUE/DIGITAL CONVERTERS; OPTICAL LOGIC ELEMENTS; OPTICS; PHYSICS; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF

A black matrix having opening at pixels with matrix array in display area, a common wire including common pads and common signal line, and gate pad in peripheral area, and an align key in outer area to correctly align interlayer thin films on an insulating substrate. Red, blue and green color filters the edge of which overlap the black matrix are formed at the pixels on the insulating substrate, and an organic insulating layer covering the black matrix and the color filters and having contact hole exposing the gate pad is formed thereon. A gate wire including a gate line connected to the gate pad through the contact hole and a gate electrode connected to the gate line is formed on the organic insulating layer, and a gate insulating layer covering the gate wire is formed on the organic insulating layer. A semiconductor pattern and ohmic contact layers are sequentially formed on the gate insulating layer of the gate electrode. A data wire including a source electrode and a drain electrode which are made of a same layer on the ohmic contact layers and separated from each other, and a data line connected to the source electrode and defining the pixels with matrix array by crossing the gate line is formed on the gate insulating layer. A passivation layer covering the data wire and having contact holes exposing the gate pad and the data pad is formed, and a pixel wire including a pixel electrode, a redundant gate pad. a redundant data pad which are respectively connected to the drain electrode, the gate pad and the data pad through the contact holes.