Thin film transistor with vertical structure

• Main Authors: GUNG, NENG-HUEI, DAI, YUAN-DUNG
• Format: Patent
• Language: English
• Published: 11.04.2003
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

This invention provides a method for fabricating a thin film transistor with a vertical lightly-doped drain structure, which comprises: forming a buffer layer on an insulative transparent substrate, forming a polysilicon layer containing source/drain regions on the buffer layer, forming an insulative layer on the polysilicon layer, forming a gate electrode on the insulative layer, forming an interlayer dielectric layer on the above-mentioned gate electrode, buffer layer and polysilicon layer, forming a via hole penetrating the above-mentioned interlayer dielectric layer to expose a portion of the source/drain region, forming an intrinsic silicon layer on the sidewall and bottom of the via hole; forming a heavily-doped silicon layer on the surface of the undoped silicon layer and covering the heavily-doped silicon layer with a metal layer.