Digital delayed phase locked loop

• Main Authors: LI, MING-SHIAN, CHEN, TSAN-HUEI, CHEN, HAN-NING, GUO, JIU-YANG
• Format: Patent
• Language: English
• Published: 11.08.2002
• Edition: 7
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY

This present invention discloses a circuit for generating a delay signal, which includes a first delay line for generating a first delay signal, a second delay line for generating a second delay signal, a delay unit for generating an internal delay signal, a first phase detector for generating a first control signal, a second phase detector for generating a second control signal. There's a delay line monitor for generating the first delay control signal and the second delay control signal, and a DTC delay unit for generating the delay signal.