Dynamic semiconductor memory, and semiconductor integrated circuit device

A DRAM having plural banks constituted of plural sub-arrays respectively and having a sense amplifier circuit shared by different sub-arrays has a column access mode in which a selected sub-array in each bank is activated to read out or write data, it has a refresh mode in which plural sub- arrays i...

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Bibliographic Details
Main Authors KOYANAGI, MASARU, TAKASE, SATORU, HARA, TAKAHIKO, NAKAGAWA, KAORU
Format Patent
LanguageEnglish
Published 21.11.2001
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A DRAM having plural banks constituted of plural sub-arrays respectively and having a sense amplifier circuit shared by different sub-arrays has a column access mode in which a selected sub-array in each bank is activated to read out or write data, it has a refresh mode in which plural sub- arrays in each bank are activated with the same timing and memory cell data is refreshed, and the number of sub-arrays activated with the same timing in one bank in a refresh mode is more than the number of sub-arrays activated in one bank in a column access mode. So provide a DRAM (dynamic random-access memory) of a non-independent bank system in which the occurrence probability of operation restriction is reduced, high-speed operation can be performed, and system performance is improved.
Bibliography:Application Number: TW200089106552