Method for manufacturing complementary metal oxide semiconductor transistor

• Main Authors: SHENG, YIUNG, CHEN, CHIN-LAI, HUANG, CHENG-TUNG, HSU, SHIHIEH
• Format: Patent
• Language: English
• Published: 07.06.2001
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The present invention provides a method for manufacturing complementary metal oxide semiconductor transistor on a semiconductor chip. The semiconductor chip comprises a substrate,a first gate on the substrate for forming the PMOS transistor of the CMOS transistor, and a second gate on the substrate for forming the NMOS transistor. The manufacturing method comprises: firstly forming a plurality of the first spacers on both sides of the two gates; next, conducting a first ion implantation process to form a first doping area in the substrate on both sides of the first gate as the heavily doping drain of the PMOS transistor; then, conducting a cleaning process to reduce the width of the plurality of the first spacers; conducting a second ion implantation process to form a second doping area in the substrate on both sides of the second gate as the heavily doping drain of the NMOS transistor; finally, forming a plurality of second spacers on both sides of the two gates, and forming the source and the drain of the PMOS transistor and the NMOS transistor in the substrate on both sides of the two gates.