Using dual-damascene method to simultaneously produce the capacitor structure and its peripheral interconnect structure of dynamic random access memory unit

• Main Authors: LIOU, HAU-JIE, YANG, FU-LIANG, LIAN, WAN-YI, YAN, TZ-SHR
• Format: Patent
• Language: English
• Published: 21.12.2000
• Edition: 7
• Subjects: ELECTRICITY

The present invention provides a method for simultaneously forming the storage node structure of DRAM unit and the interconnect structure of peripheral area of DRAM chip. The method is characterized by using dual-damascene process whose first plug process is used to produce the storage node and interconnect structure, then using the second damascene process to produce the plug structure contacting underneath storage node and interconnect structure. The present invention is also characterized by using SAC window which allows completing the forming of SAC storage node structure.