A clock phase correction circuit

A clock phase correction circuit for a semiconductor memory device reduces all lock ranges by using a half-mixer to a conventional delay locked loop (DLL) circuit, and thus generates a clock signal having a fast lock time and a very small jitter. In order to achieve this objective, a track portion h...

Full description

Saved in:
Bibliographic Details
Main Author SUNG, JUN-BAE
Format Patent
LanguageEnglish
Published 11.12.2000
Edition7
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:A clock phase correction circuit for a semiconductor memory device reduces all lock ranges by using a half-mixer to a conventional delay locked loop (DLL) circuit, and thus generates a clock signal having a fast lock time and a very small jitter. In order to achieve this objective, a track portion having a plurality of phase converters and one half-mixer is provided between an input terminal of external clock and an input terminal of a delay means of the conventional DLL circuit, and approaches the phase of the external clock to a phase of the feedback clock. A phase difference between the corrected signal and the feedback clock is then reduced by the conventional DLL circuit. As a result, lock time becomes shorter, and the magnitude of a jitter becomes reduced.
Bibliography:Application Number: TW19990108592