Arrangement to control parallel lines of a memory-cell arrangement

To control parallel lines, for example, bit-lines (BLn) of a memory-cell arrangement, said bit-lines include doped areas that are arranged in a semiconductor substrate, then some bit-lines (BLn) are electrically connected one another and also connected with a common node (K). Some selection-lines (A...

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Main Authors REISINGER, HANS, HOFMANN, FRANZ, KRAUTSCHNEIDER, WOLFGANG, VON BASSE, PAUL-WERNER, WILLER, JOSEF
Format Patent
LanguageChinese
English
Published 01.07.1999
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:To control parallel lines, for example, bit-lines (BLn) of a memory-cell arrangement, said bit-lines include doped areas that are arranged in a semiconductor substrate, then some bit-lines (BLn) are electrically connected one another and also connected with a common node (K). Some selection-lines (ALn) are provided vertically to said bit-lines (BLn). MOS-transistors (M1, M2) are arranged at the cross-points, said transistors are connected in series along one of the lines (BLn), the gate-electrodes of said transistors are constructed through the corresponding selection-lines (ALn). At least one MOS-transistor (M1) in each of the parallel lines (BLn) has a higher turn-on voltage than the others.
Bibliography:Application Number: TW199786117354