Delay stage with steep edges

A delay stage with steep edges, having the first flip (M1, M2) and the second flip (M3, M4) in serial, being the input of the first flip match the input of the delay class (E) and the output of the second flip to the output of the delay class (D), and in connection as p-channel transistor (M3) of th...

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Bibliographic Details
Main Authors THEWES, ROLAND, BOLLU, MICHAEL, SCHMITT-LANDSIEDEL, DORIS, VON BASSE, PAUL-WERNER
Format Patent
LanguageChinese
English
Published 11.01.1999
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS
PULSE TECHNIQUE
RESONATORS
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Summary:A delay stage with steep edges, having the first flip (M1, M2) and the second flip (M3, M4) in serial, being the input of the first flip match the input of the delay class (E) and the output of the second flip to the output of the delay class (D), and in connection as p-channel transistor (M3) of the second flip at between the gate and the delay output, in connection as n-channel transistor (M6) with the capacitor between the delay class output and the second flip n-channel transistor gate.
Bibliography:Application Number: TW19970112149