Semiconductor package with binding reinforcement layer

Provided is a semiconductor package including a first wiring structure including a plurality of first wiring patterns respectively including a plurality of first lower surface connection pads and a plurality of first upper surface connection pads, a second wiring structure including a plurality of s...

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Bibliographic Details
Main Author HEO, YU-SEON
Format Patent
LanguageChinese
English
Published 16.05.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Provided is a semiconductor package including a first wiring structure including a plurality of first wiring patterns respectively including a plurality of first lower surface connection pads and a plurality of first upper surface connection pads, a second wiring structure including a plurality of second wiring patterns respectively including a plurality of second lower surface connection pads and a plurality of second upper surface connection pads, a semiconductor chip arranged between the first wiring structure and the second wiring structure, a plurality of connection structures connecting some of the plurality of first upper surface connection pads to the plurality of second lower surface connection pads, and arranged adjacent to the semiconductor chip, and a binding reinforcement layer on side surfaces of each of the plurality of connection structures and at least a portion of the semiconductor chip.
Bibliography:Application Number: TW202312136648