An apparatus, a method and a system for performing instructions and logic to perform floating-point and integer operations for machine learning
One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.
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Main Authors | , , , , , , , , , , , , , , , , , , |
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Format | Patent |
Language | Chinese English |
Published |
16.05.2024
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Subjects | |
Online Access | Get full text |
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Summary: | One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation. |
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Bibliography: | Application Number: TW202413103959 |