An apparatus, a method and a system for performing instructions and logic to perform floating-point and integer operations for machine learning

One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.

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Bibliographic Details
Main Authors TANG, PING, SHPEISMAN, TATIANA, LIN, TSUNG-HAN, RANGANATHAN, VASANTH, MATHEW, SANU, KOKER, ALTUG, STRICKLAND, MICHAEL, NURVITADHI, ERIKO, VEMBU, BALAJI, CHEN, XIAO-MING, APPU, ABHISHEK, RAY, JOYDEEP, GALOPPO VON BORRIES, NICOLAS, KAUL, HIMANSHU, YAO, AN-BANG, SINHA, KAMAL, JAHAGIRDAR, SANJEEV, BARIK, RAJKISHORE, ANDERS, MARK
Format Patent
LanguageChinese
English
Published 16.05.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
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Summary:One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.
Bibliography:Application Number: TW202413103959