Semiconductor device and forming method thereof

A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain re...

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Main Authors LIN, WEING, LIN, MENG-YU, CHEN, SZU-HUA, CHENG, CHUN-FU, LIAO, SZUYA, HUANG, JUIIEN, HUANG, HSIANG-HUNG, WANG, CHENG-YIN, WU, TING-YUN, HO, WEI-DE, HUNG, HSIN-YANG, HU, KUAN-KAN, YOU, WEI-XIANG, TZENG, WEING
Format Patent
LanguageChinese
English
Published 16.03.2024
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Summary:A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. The interconnect structure includes: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being in the gate isolation structure; an opening
Bibliography:Application Number: TW202312111647