Address translation prefetching for input/output devices
In one example of the present technology, an input/output memory management unit (lOMMU) of a computing device is configured to: receive a prefetch message including a virtual address from a central processing unit (CPU) core of a processor of the computing device; perform a page walk on the virtual...
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Main Authors | , |
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Format | Patent |
Language | Chinese English |
Published |
16.12.2023
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Subjects | |
Online Access | Get full text |
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Summary: | In one example of the present technology, an input/output memory management unit (lOMMU) of a computing device is configured to: receive a prefetch message including a virtual address from a central processing unit (CPU) core of a processor of the computing device; perform a page walk on the virtual address through a page table stored in a main memory of the computing device to obtain a prefetched translation of the virtual address to a physical address; and store the prefetched translation of the virtual address to the physical address in a translation lookaside buffer (TLB) of the lOMMU. |
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Bibliography: | Application Number: TW202312116399 |