Semiconductor device and forming method thereof

• Main Authors: CHOU, CHI-YU, PAI, YUEHING, MORE, SHAHAJI B, TAN, LUN-KUANG, CHANG, CHENG-WEI
• Format: Patent
• Language: Chinese; English
• Published: 16.11.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Nanostructure transistors are formed in a manner that may reduce the likelihood of source/drain region merging in the nanostructure transistors. In a top-down view of a nanostructure transistor described herein, source/drain regions on opposing sides of a nanostructure channel of the nanostructure transistor are staggered such that distance between the source/drain regions is increased. This reduces the likelihood of the source/drain regions merging, which reduces the likelihood of failures and/or other defects forming in the nanostructure transistor. Accordingly, staggering the source/drain regions, as described herein, may facilitate the miniaturization of semiconductor devices that include nanostructure transistors while maintaining and/or increasing the semiconductor device yield of the semiconductor devices.