Semiconductor structures and methods of formation

Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.

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Bibliographic Details
Main Authors KUO, CHIA-PANG, LIU, YAO-MIN, LEE, YA-LIEN, CHEN, KUANIA, CHIN, SHUNG, PENG, HSIN-YING, HUANG, JAU-JIUN, CHI, CHIHIEN
Format Patent
LanguageChinese
English
Published 01.10.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.
Bibliography:Application Number: TW202312100354