Double-sided interconnected embedded chip packaging structure and manufacturing method thereof

• Main Authors: HUANG, BEN-XIA, FENG, JIN-DONG, HONG, YE-JIE, CHEN, XIAN-MING
• Format: Patent
• Language: Chinese; English
• Published: 01.06.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A double-sided interconnected embedded chip packaging structure disclosed by the present invention comprises a first insulating layer and a second insulating layer, the first insulating layer comprises first conduction copper column layers penetrating through the first insulating layer along the height direction and first chips located between adjacent first conduction copper columns, the first chips are mounted in the lower surface of the first insulating layer, and the first conduction copper column layers penetrate through the second insulating layer along the height direction. The second insulating layer comprises a first conduction line layer and a heat dissipation copper surface which are located in the upper surface of the second insulating layer, a second conduction copper column layer is arranged on the first conduction line layer, the first conduction copper column layer is connected with the first conduction line layer, and the heat dissipation copper surface is connected with the back surface of t