Clock data calibration circuit

• Main Authors: TSENG, YU-HSIN, LIN, ZHI-XIN, CHANG, YUNG-SUNG, GAO, JING-ZHI
• Format: Patent
• Language: Chinese; English
• Published: 01.11.2022
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A clock data calibration circuit includes a first comparator, a multi-phase clock generator, a plurality of samplers, a plurality of data comparator and a data selector. The first comparator compares a first input data with a second input data to generate a data signal. The multi-phase clock generator generates a plurality of clock signals, and the clock signals are divided into a plurality of clock groups. The sampler samples the data signal according to the clock groups to respectively generator a plurality of first sampled data signal groups. The data comparators respectively sample the first sampled data groups according to a plurality of selected clocks to generate a plurality of second sampled data groups. Each data comparator generates a plurality of status flags according to a variation state of a plurality of second sampled data. The data selector generates a plurality of output data signals according to the status flags.