Configuration and method for NAND memory programming design

In a method for programming a memory element, prohibition information is stored in the first latch structure and the second latch structure. The first state programming voltage is applied to the data line of the storage unit of the memory device, thereby programming the storage unit to the first sta...

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Bibliographic Details
Main Author WAN, WEI-JUN
Format Patent
LanguageChinese
English
Published 16.08.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:In a method for programming a memory element, prohibition information is stored in the first latch structure and the second latch structure. The first state programming voltage is applied to the data line of the storage unit of the memory device, thereby programming the storage unit to the first state. The first state verification voltage is applied to the data line of the storage unit to perform the first state verification operation on the storage unit. Based on the first target value, the first state verification operation verifies the first state threshold voltage of the storage unit and also generates failure mode data of the first state verification operation. Then the failure mode data is stored in the second latch structure. In addition, the first electrical level adjusted verification voltage is applied to the data lines of a part of the storage units which have failed the first electrical level verification operation, thereby performing the first electrical level adjusted verification operation.
Bibliography:Application Number: TW202211117296