Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits

• Main Authors: KANG, SEUNG HYUK, BOYNAPALLI, VENUGOPAL, SHARMA, DEEPAK, CHAVA, BHARANI, NALLAPATI, GIRIDHAR, FENG, PEI-JIE, LIM, HYEOK-JIN, RIM, KERN, SONG, STANLEY SEUNGCHUL, CHIDAMBARAM, PERIANNAN, KIM, JONGHAE, VANG, FOUA
• Format: Patent
• Language: Chinese; English
• Published: 01.08.2022
• Subjects: BASIC ELECTRIC ELEMENTS; BASIC ELECTRONIC CIRCUITRY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; PULSE TECHNIQUE; SEMICONDUCTOR DEVICES

Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.