Processor and processor architecture thereof

Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a c...

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Main Authors OULD-AHMED-VALL, ELMOUSTAPHA, GROCHOWSKI, EDWARD, HUFF, THOMAS, PAPWORTH, DAVID, CHAPPELL, ROBERT, SOTOUDEH, SEYED YAHYA, TOLL, BRET, BRANDT, JASON, CORBAL, JESUS, GUNTHER, STEPHEN, SINGHAL, RONAK, GUY, BUFORD, HUGHES, CHRISTOPHER, RAPPOPORT, LIHU, ALLEN, JAMES
Format Patent
LanguageChinese
English
Published 16.05.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
Bibliography:Application Number: TW202211102764