Oxide liner stress buffer

A through-wafer via substrate includes a substrate having an intermediate layer and a bonding layer formed on a surface of the intermediate layer. A via cavity extends through the bonding layer and into the intermediate layer, and a stress buffer liner is deposited directly on inner sidewalls and a...

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Bibliographic Details
Main Authors FRANDSEN, CHRISTINE, DRAB, JOHN J, CLARKE, ANDREW
Format Patent
LanguageChinese
English
Published 01.06.2021
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A through-wafer via substrate includes a substrate having an intermediate layer and a bonding layer formed on a surface of the intermediate layer. A via cavity extends through the bonding layer and into the intermediate layer, and a stress buffer liner is deposited directly on inner sidewalls and a base of the via cavity. An electrically conductive through-wafer via is disposed in the via cavity such that the stress buffer liner is interposed completely between the intermediate layer and the through-wafer via.
Bibliography:Application Number: TW20209129499