Synchronous memory bus access to storage media

A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, ope...

Full description

Saved in:
Bibliographic Details
Main Authors ROSS, FRANK F, STONELAKE, PAUL, SILBERMANN, BRYAN T
Format Patent
LanguageChinese
English
Published 16.10.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.
Bibliography:Application Number: TW20198103272