Architecture for 3-D NAND memory
Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.
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| Main Authors | , |
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| Format | Patent |
| Language | Chinese English |
| Published |
01.02.2019
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| Subjects | |
| Online Access | Get full text |
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| Abstract | Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area. |
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| AbstractList | Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area. |
| Author | TANAKA, TOMOHARU MOROOKA, MIDORI |
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| Snippet | Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the... |
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| Title | Architecture for 3-D NAND memory |
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