Thin fan-out type multi-chip stacked package

• Main Authors: CHANG, CHIA-WEI, CHUANG, YONGNG, LIN, YU-TSO
• Format: Patent
• Language: Chinese; English
• Published: 01.08.2018
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Disclosed is a thin fan-out multi-chip stacked package. A molding compound encapsulates a chip stacked assembly and a plurality of vertically connecting components. The chip stacked assembly comprises a plurality of chips stacked to each other, where the electrodes of the chips and the active surface of one of the plurality of chips are exposed. Preferably, the plurality of chips are staggered stacked with Z-shaped deviation. The vertically connecting components are coupled onto the electrodes. A planar surface of the molding compound is adjacent to the exposed active surface. In this way, the vertically connecting components have a plurality of coupling surfaces coplanar and exposed from the planar surface of the molding compound. A redistribution layer (RDL) structure is formed on the planar surface. A passivation layer covers the planar surface and has a plurality of pattern holes to expose the coupling surfaces. And, a plurality of fan out traces on the passivation layer may be coupled to the bonding surf