Memory cell

A memory cell includes a coupling device, a read transistor, a first read selection transistor, a second read selection transistor, an erase device, a program transistor, and a program selection transistor. The coupling device is formed on a first doped region. The erase device is formed on a second...

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Bibliographic Details
Main Authors CHANG, WEIN, WANG, SHIHN, LO, CHUN-YUAN
Format Patent
LanguageChinese
English
Published 16.06.2018
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory cell includes a coupling device, a read transistor, a first read selection transistor, a second read selection transistor, an erase device, a program transistor, and a program selection transistor. The coupling device is formed on a first doped region. The erase device is formed on a second doped region. The read transistor, the first read selection transistor, the second read selection transistor, the program transistor, and the program selection transistor are formed on a third doped region. A gate terminal of the coupling device is coupled to a common floating gate. A gate terminal of the erase device is coupled to the common floating gate. During a program operation, electrical charges are moved from the program selection transistor to the common floating gate. During an erase operation, electrical charges are moved from the common floating gate to the erase device.
Bibliography:Application Number: TW20176108098