Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks

• Main Authors: HALTER, STEVEN JOHN, SOMASUNDARAM, MANOKANTHAN, DENA, SINA, PODAIMA, JASON EDWARD, AVOINNE, CHRISTOPHE DENIS BERNARD, RAMKUMAR, MYIL, RYCHLIK, BOHUSLAV, PAL, DIPTI RANJAN, SUBRAMANIAM GANASAN, JAYA PRAKASH, WIERCIENSKI, PAUL CHRISTOPHER JOHN
• Format: Patent
• Language: Chinese; English
• Published: 16.10.2017
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.