A patterned pad to create a virtual solder mask for wafer-level chip-scale packages

Methods and devices for a patterned pad to create a virtual solder mask for wafer-level chip-scale packages may include a contact pad formed on a semiconductor die, the contact pad including: a center pad, a trace, and a first set of spokes extending out from the center pad. A brace may surround a p...

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Bibliographic Details
Main Authors BERRY, CHRISTOPHER J, RINNE, GLENN, BALOGLU, BORA
Format Patent
LanguageChinese
English
Published 16.06.2017
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Methods and devices for a patterned pad to create a virtual solder mask for wafer-level chip-scale packages may include a contact pad formed on a semiconductor die, the contact pad including: a center pad, a trace, and a first set of spokes extending out from the center pad. A brace may surround a portion of the first spoke pattern and the center pad. A solder ball may be formed on the center pad and the first spoke pattern but not on the brace. The center pad may comprise a circular metal disc or ring. A second spoke pattern including one or more spokes may extend out from the brace. A second brace may surround the first and second spoke patterns, the brace, and the center pad. The first and second spoke patterns may have different widths and may extend at different angles with respect to the center pad.
Bibliography:Application Number: TW20170104408