Method of decomposing layout of semiconductor device and method of manufacturing semiconductor device using the same

Methods of decomposing a layout of a semiconductor device and methods of manufacturing a semiconductor device using the same are provided. In the method of decomposing the layout of the semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines a...

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Bibliographic Details
Main Authors JUNG, JI-YOUNG, HWANG, SUNG-WOOK, KIM, DONG-GYUN, KANG, DAE-KWON, YANG, JAE-SEOK
Format Patent
LanguageChinese
English
Published 16.03.2016
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
BASIC ELECTRIC ELEMENTS
CALCULATING
CINEMATOGRAPHY
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:Methods of decomposing a layout of a semiconductor device and methods of manufacturing a semiconductor device using the same are provided. In the method of decomposing the layout of the semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.
Bibliography:Application Number: TW20154120415