Method and system for error management in a memory device

A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity err...

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Bibliographic Details
Main Authors BAINS, KULJIT S, BRZEZINSKI, DENNIS W, WILLIAMS, MICHAEL, HALBERT, JOHN B, ZIMMERMAN, DAVID J
Format Patent
LanguageChinese
English
Published 01.02.2016
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.
Bibliography:Application Number: TW20154120315